As integrated circuit package assemblies become smaller and more complex it has become challenging to efficiently route signals between different components. Increasing the length and/or complexity of conductive pathways may limit bandwidth between components such as a processor and memory. Also, lengthy and/or complicated power delivery pathways can increase losses and decrease overall power efficiency. Current techniques tend to place components in a single plane, establishing effective minimum lengths for conductive pathways based on the size and spatial arrangement of the components to be connected.